MAX5935EAX+【PDF 20/44 页】IC CTRLR POWER QUAD 36-SSOP

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Bit Transfer

Each clock pulse transfers one data bit (Figure 8). The

data on SDA must remain stable while SCL is high.

Acknowledge

The acknowledge bit is a clocked 9th bit (Figure 9),

which the recipient uses as a handshake receipt of each

byte of data. Thus, each byte effectively transferred

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA (or the SDAOUT

in the 3-wire interface) during the acknowledge clock

pulse, such that the SDA line is stable low during the

high period of the clock pulse. When the master trans-

mits to the MAX5935, the MAX5935 generates the

acknowledge bit. When the MAX5935 transmits to the

master, the master generates the acknowledge bit.

Slave Address

The MAX5935 has a 7-bit long slave address (Figure

10). The bit following the 7-bit slave address (bit eight)

is the R/W bit, which is low for a write command and

high for a read command.

010 always represent the first three bits (MSBs) of the

MAX5935 slave address. Slave address bits A3, A2,

A1, and A0 represent the states of the MAX5935s A3,

A2, A1, and A0 inputs, allowing up to sixteen MAX5935

devices to share the bus. The states of the A3, A2, A1,

and A0 latch in upon the reset of the MAX5935 into reg-

ister R11h. The MAX5935 monitors the bus continuous-

ly, waiting for a START condition followed by the

MAX5935s slave address. When the MAX5935 recog-

nizes its slave address, it acknowledges and is then

ready for continued communication.

Global Addressing and Alert Response Protocol

The global address call is used in writing mode to write

the same register to multiple devices (address 0x60). In

read mode (address 0x61), the global address call is

used as the Alert Response address. When responding

to a global call, the MAX5935 puts out on the data line its

own address whenever its interrupt is active and so does

every other device connected to the SDAOUT line that

has an active interrupt. After every bit is transmitted, the

MAX5935 checks that the data line effectively corre-

sponds to the data it is delivering. If it is not, it then backs

off and frees the data line. This litigation protocol always

allows the part with the lowest address to complete the

transmission. The microcontroller can then respond to

the interrupt and take proper actions. The MAX5935

does not reset its own interrupt at the end of the Alert

Response protocol. The microcontroller has to do it by

clearing the event register through their CoR addresses

or activating the CLR_INT pushbutton.

Quad Network Power Controller

for Power-Over-LAN

20 ______________________________________________________________________________________

Figure 9. Acknowledge

SCL

SDA

BY TRANSMITTER

CLOCK PULSE FOR ACKNOWLEDGEMENT

START CONDITION

SDA

BY RECEIVER

Figure 10. Slave Address

SDA

SCL

MSB

LSB

ACK

R/W

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